Organic light-emitting display apparatus and method of repairing the same

ABSTRACT

Provided is an organic light-emitting display apparatus and a method of repairing the same. The organic light-emitting display apparatus includes: an emission device comprising a plurality of sub-emission devices; an emission pixel circuit configured to supply a driving current to the emission device; a dummy pixel circuit configured to supply the driving current to the emission device; and a repair line coupling the emission device to the dummy pixel circuit, wherein the emission device is configured to receive the driving current from the emission pixel circuit or the dummy pixel circuit.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to and the benefit of Korean PatentApplication Nos. 10-2013-0057959 and 10-2013-0068638, filed on May 22,2013 and Jun. 14, 2013, respectively, in the Korean IntellectualProperty Office, the disclosures of which are incorporated herein intheir entirety by reference.This application is a reissue application ofU.S. Pat. No. 9,911,799, issued on Mar. 6, 2018, which claims priorityto and the benefit of Korean Patent Application Nos. 10-2013-0057959 and10-2013-0068638, filed on May 22, 2013 and Jun. 14, 2013, respectively,in the Korean Intellectual Property Office, the disclosures of which areincorporated herein in their entirety by reference.

BACKGROUND

1. Field

Embodiments of the present invention relate to an organic light-emittingdisplay apparatus and a method of repairing the same.

2. Description of the Related Art

In an organic light-emitting display apparatus, when a pixel isdefective, the pixel may emit light all the time or may display black(e.g., may not emit light), regardless of a scan signal and a datasignal applied to the pixel. Pixels that emit light all the time,regardless of the scan or data signals, are regarded as bright spots (orhot spots). By contrast, pixels that do not emit light (e.g., displayedin black), regardless of the scan or data signals, is regarded as a darkspot (or a black spot).

As a circuit in the pixel becomes more complex, bright spots or darkspots due to circuit defects may not be easily solved or prevented.

SUMMARY

Embodiments of the present invention provide a display apparatus forforming a redundancy pattern in each column of pixels on a panel andnormally driving a defective pixel by using the redundancy pattern.

According to an embodiment of the present invention, there is providedAn organic light-emitting display apparatus including: an emissiondevice including a plurality of sub-emission devices; an emission pixelcircuit configured to supply a driving current to the emission device; adummy pixel circuit configured to supply the driving current to theemission device; and a repair line coupling the emission device to thedummy pixel circuit, wherein the emission device is configured toreceive the driving current from the emission pixel circuit or the dummypixel circuit.

Each of the plurality of sub-emission devices may include: a lowerelectrode among a plurality of separated lower electrodes; an upperelectrode commonly facing the plurality of separated lower electrodes;and an emission layer between the lower electrode and the upperelectrode, wherein the plurality of separated lower electrodes areelectrically coupled to each other through an electrode connectionwiring.

The electrode connection wiring may include at least one of metal,amorphous silicon, crystalline silicon, and an oxide semiconductor.

The electrode connection wiring may be at a same layer and of a samematerial as an active layer of the emission pixel circuit.

The electrode connection wiring may be integrally formed with theplurality of separated lower electrodes.

The electrode connection wiring may include: a plurality of firstconnection units coupled to the plurality of separated lower electrodes;a second connection unit coupled to the emission pixel circuit; and aplurality of cut nodes between the first connection units and the secondconnection unit, wherein the cut nodes are cut to electrically isolatethe plurality of separated lower electrodes from each other.

The electrode connection wiring may be coupled to the plurality ofseparated lower electrodes in each of the first connection units througha first contact hole and may be coupled to the emission pixel circuitthrough a second contact hole in the second connection unit.

The organic light-emitting display apparatus may further include atleast one circuit wiring having one end coupled to the emission pixelcircuit and another end coupled to the second connection unit, whereinthe at least one circuit wiring may be configured to be cut toelectrically isolate the emission pixel circuit from the emissiondevice.

The organic light-emitting display apparatus may further include a firstrepair connection wiring having one end coupled to the repair line andanother end overlapping with a first short wiring coupled to one of thefirst connection units; and an insulating layer between the first repairconnection wiring and the first short wiring, wherein the first repairconnection wiring is configured to be coupled to the first short wiringutilizing a laser beam.

Each of the first repair connection wiring and the first short wiringmay be at a same layer and of a same material as respective conductivelayers formed on different layers of the emission pixel circuit.

The dummy pixel circuit may be on at least one row among first and lastrows of each column, or at least one column among first and last columnsof each row.

The emission pixel circuit may be in a display area and the dummy pixelcircuit is in a non-display area.

The emission pixel circuit and the dummy pixel circuit may have a samecomponent structure and function.

The dummy pixel circuit may be coupled to the emission device through asecond repair connection wiring having one end coupled to the repairline and another end overlapping with a second short wiring coupled tothe dummy pixel circuit, wherein an insulating layer may be between thesecond repair connection wiring and the second short wiring.

The repair line may be coupled to a power voltage line through a powerconnection wiring and may be configured to be electrically isolated fromthe power voltage line by cutting the power connection wiring.

The repair line may be in each column or row.

The emission pixel circuit may include: a first transistor configured totransfer a data signal in response to a scan signal; a capacitorconfigured to be charged with a voltage corresponding to the datasignal; and a second transistor configured to transfer a driving currentcorresponding to the voltage charged in the capacitor to the emissiondevice.

The emission pixel circuit may include: a first transistor configured toreceive a data signal from a data line in response to a scan signal; asecond transistor configured to transfer a driving current correspondingto the data signal to the emission device; a third transistor configuredto diode-connect the second transistor; a first capacitor configured tobe charged with a voltage corresponding to the data signal; and a secondcapacitor connected to one electrode of the first capacitor and a gateelectrode of the second transistor.

The emission pixel circuit may further include: a fourth transistorconnected to between the first transistor and the one electrode of thefirst capacitor; a fifth transistor connected to between the data lineand the one electrode of the first capacitor; and a third capacitorhaving one electrode connected to a node between the first transistorand the fourth transistor and another electrode connected to a gateelectrode of the fifth transistor.

The emission pixel circuit may include: a first transistor configured toreceive a data signal from a data line in response to a scan signal; asecond transistor configured to transfer a driving current correspondingto the data signal to the emission device; a third transistor configuredto diode-connect the second transistor; a fourth transistor connected tobetween the first transistor and the second transistor; a fifthtransistor connected to between the second transistor and the emissiondevice; a sixth transistor connected to between a gate electrode of thesecond transistor and an initial power; a first capacitor connected tobetween the gate electrode of the second transistor and a first powersource; and a second capacitor having one electrode connected to a nodebetween the first transistor and the fourth transistor and anotherelectrode connected to a second power source.

The dummy pixel circuit may be configured to supply the driving currentto the emission device at a predetermined time.

The dummy pixel circuit may be configured to supply a same data signalas that supplied by the emission pixel circuit to the emission device.

The plurality of sub-emission devices may include: a first sub-emissiondevice including a first lower electrode, an upper electrode facing thefirst lower electrode, and a first emission layer between the firstlower electrode and the upper electrode; and a second sub-emissiondevice including a second lower electrode, the upper electrode facingthe second lower electrode, and a second emission layer between thesecond lower electrode and the upper electrode, wherein the first lowerelectrode and the second lower electrode are coupled to each otherthrough an electrode connection wiring.

The electrode connection wiring may include: a first connection unitcoupled to the first lower electrode; a second connection unit coupledto the second lower electrode; a third connection unit coupled to theemission pixel circuit; a first node between the first connection unitand the third connection unit and configured to be cut to electricallyisolate the first sub-emission device from the emission pixel circuit;and a second node between the second connection unit and the thirdconnection unit and configured to be cut to electrically isolate thesecond sub-emission device from the emission pixel circuit.

The organic light-emitting display apparatus may further include a firstrepair connection wiring having one end coupled to the repair line andanother end overlapping with a first short wiring coupled to the firstconnection unit; a first insulating layer between the first repairconnection wiring and the first short wiring, wherein the first repairconnection wiring is configured to be coupled to the first short wiringutilizing a laser beam; a second repair connection wiring having one endcoupled to the repair line and another end overlapping with a secondshort wiring coupled to the dummy pixel circuit; and a second insulatinglayer between the second repair connection wiring and the second shortwiring, wherein the second repair connection wiring is configured to becoupled to the second short wiring utilizing the laser beam.

According to another embodiment of the present invention there isprovided a method of repairing a defective pixel in an organic lightemitting display apparatus, the organic light emitting display apparatusincluding a plurality of emission pixels including an emission deviceincluding a plurality of sub-emission devices, the sub-emission devicesbeing configured to receive a corresponding driving current from one ofan emission pixel circuit and a dummy pixel circuit, the methodincluding: connecting the defective pixel to the dummy pixel circuitthrough a repair line; and after connecting the defective pixel to thedummy pixel circuit, if the defective pixel does not normally emitlight, separating the plurality of sub-emission devices.

The separating of the plurality of sub-emission devices may include:cutting between a connection unit of the emission pixel circuit and aconnection unit of each of lower electrodes of the plurality ofsub-emission devices in an electrode connection wiring that couples thelower electrodes to each other.

The method may further include after coupling the defective pixel to thedummy pixel circuit, if the defective pixel normally emits light,separating the emission pixel circuit and the emission device from eachother.

The separating of the emission pixel circuit and the emission device mayinclude: cutting at least one wiring coupled between the emission pixelcircuit and the lower electrodes of the emission device.

The coupling of the defective pixel to the dummy pixel circuit mayinclude: shorting a first short wiring coupled to the emission deviceand a second short wiring coupled to the dummy pixel circuit by:irradiating a laser beam onto a first repair connection wiring havingone end coupled to the repair line and another end overlapping with thefirst short wiring, wherein a first insulating layer is between thefirst repair connection wiring and the first short wiring, andirradiating the laser beam onto a second repair connection wiring havingone end coupled to the repair line and another end overlapping with thesecond short wiring with a second insulating layer between the secondrepair connection wiring and the second short wiring.

The method may further include separating a defective sub-emissiondevice among a plurality of sub-emission devices of the defective pixelfrom the other sub-emission devices.

The separating of the defective sub-emission device among the pluralityof sub-emission devices of the defective pixel from the othersub-emission devices may include: cutting between a connection unit of alower electrode of the defective sub-emission device and a connectionunit of the emission pixel circuit in an electrode connection wiringthat couples lower electrodes of the plurality of sub-emission devicesto each other.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and aspects of the present invention willbecome more apparent by describing in detail exemplary embodimentsthereof with reference to the attached drawings in which:

FIG. 1 is a block diagram of a display apparatus according to anembodiment of the present invention;

FIGS. 2 through 4 are schematic diagrams of examples of a display panelillustrated in FIG. 1 ;

FIG. 5 is a diagram for describing a method of repairing a defectivepixel by using a plurality of repair lines of the display panel of FIG.2 , according to an embodiment of the present invention;

FIGS. 6 and 7 show waveforms of scan signals and data signals providedto the display panel repaired by using the method illustrated in FIG. 5;

FIG. 8 is a diagram for describing a method of repairing a defectivepixel by using a plurality of repair lines of the display panel of FIG.3 , according to another embodiment of the present invention;

FIGS. 9 and 10 show waveforms of scan signals and data signals providedto the display panel repaired by using the method illustrated in FIG. 8;

FIG. 11 is a diagram for describing a method of repairing a defectivepixel by using a plurality of repair lines of the display panel of FIG.4 , according to another embodiment of the present invention;

FIGS. 12 and 13 show waveforms of scan signals and data signals providedto the display panel repaired by using the method illustrated in FIG. 11;

FIG. 14 is a schematic diagram of an emission pixel according to anembodiment of the present invention;

FIG. 15 is a plan view of an emission device of the emission pixel ofFIG. 14 ;

FIG. 16 is a cross-sectional view taken along the line A-A′ of FIG. 15 ;

FIG. 17 is a schematic diagram of a dummy pixel according to anembodiment of the present invention;

FIG. 18 is a plan view of a part of the dummy pixel of FIG. 17 ;

FIG. 19 is a cross-sectional view taken along the line B-B′ of FIG. 18 ;

FIG. 20 is a flowchart for explaining a method of repairing a defectivepixel, according to an embodiment of the present invention;

FIGS. 21 through 26 are diagrams for explaining a method of repairing adefective pixel in a case of a visible defect of FIG. 20 , according toembodiments of the present invention;

FIGS. 27 through 29B are diagrams for explaining a method of repairing adefective pixel in the case of the invisible defect of FIG. 20 ,according to embodiments of the present invention;

FIGS. 30A through 32 are diagrams for explaining a method of repairing adefective pixel in the case of the invisible defect of FIG. 20 ,according to embodiments of the present invention;

FIGS. 33 through 36 are circuit diagrams of an emission pixel accordingto embodiments of the present invention;

FIG. 37 is a schematic diagram of a display panel, according to anotherembodiment of the present invention;

FIG. 38 is a circuit diagram of an emission pixel according to anotherembodiment of the present invention;

FIG. 39 is a plan view of an emission pixel including a pixel circuit ofFIG. 38 ;

FIG. 40 is a plan view of a dummy pixel including a pixel circuit ofFIG. 38 ;

FIG. 41 is a plan view of an emission device of an emission pixelaccording to another embodiment of the present invention;

FIG. 42 is a cross-sectional view taken along a line C-C′ of FIG. 41 ;and

FIG. 43 is a cross-sectional diagram of an organic light emittingdisplay apparatus including an emission pixel, according to anembodiment of the present invention.

DETAILED DESCRIPTION

Hereinafter, embodiments of the present invention will be described insome detail by explaining embodiments of the invention with reference tothe attached drawings. Like reference numerals in the drawings denotelike elements. In the following description of the present invention, adetailed description of known functions and configurations incorporatedherein will be omitted when it may make the subject matter of thepresent invention unclear.

In the drawings, the thicknesses of layers and regions are exaggeratedfor clarity. It will be understood that when a layer is referred to asbeing “on” another layer or substrate, it can be directly on the otherlayer or substrate, or intervening layers may also be present.

It will be further understood that the terms “comprises” and/or“comprising” when used in this specification, specify the presence ofstated features, integers, steps, operations, elements, and/orcomponents, but do not preclude the presence or addition of one or moreother features, integers, steps, operations, elements, components,and/or groups thereof. Also, the term “on” refers to an upper or lowerside of a target and does not always mean an upper side in a directionof gravity.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of the present invention.

As used herein, the term “and/or” includes any and all combinations ofone or more of the associated listed items. Expressions such as “atleast one of,” when preceding a list of elements, modify the entire listof elements and do not modify the individual elements of the list.

FIG. 1 is a block diagram of a display apparatus 100 according to anembodiment of the present invention.

Referring to FIG. 1 , the display apparatus 100 includes a display panel10 including a plurality of pixels, a scan driving unit 20, a datadriving unit 30, and a control unit 40. The scan driving unit 20, thedata driving unit 30, and the control unit 40 may be separately formedon different semiconductor chips, or may be integrated on a singlesemiconductor chip. Also, the scan driving unit 20 may be formed on thesame substrate as the display panel 10.

A plurality of scan lines SL extending in a horizontal direction and aplurality of the data lines DL extending in a vertical direction andperpendicularly crossing the scan lines SL are formed on the displaypanel 10. Also, a plurality of repair lines RL extending almost parallelor substantially parallel with and spaced apart from the data lines DLand perpendicularly crossing the scan lines SL are formed on the displaypanel 10. A plurality of pixels P aligned in a matrix-like shape areformed where the scan lines SL, the data lines DL, and the repair linesRL cross each other.

Although the data line DL is formed at a right side of the pixel P andthe repair line RL is formed at a left side of the pixel P in FIG. 1 ,the present invention is not limited thereto. For example, the positionsof the data line DL and the repair line RL may be switched according tothe design and function of the display panel 10. One or more repairlines RL may be formed in each pixel column. The one or more repairlines RL may be formed or arranged in parallel to the scan lines SLaccording to a pixel design so that the one or more repair lines RL maybe formed or arranged in each pixel row. Although not shown in FIG. 1 ,additional signal or voltage lines such as a plurality of emissioncontrol lines for providing an emission control signal, aninitialization voltage line for providing an initialization voltage, anda driving voltage line for providing a power voltage may be additionallyformed or arranged on the display panel 10.

The scan driving unit 20 may generate and sequentially provide scansignals via the scan lines SL to the display panel 10.

The data driving unit 30 may sequentially provide data signals via thedata lines DL to the display panel 10. The data driving unit 30transforms input image data DATA, input from the control unit 40 andhaving a grayscale (e.g., grey levels), into a voltage or current datasignal.

The control unit 40 generates and transmits a scan control signal SCSand a data control signal DCS respectively to the scan driving unit 20and the data driving unit 30. As such, the scan driving unit 20sequentially provides or activates scan signals to the scan lines SL,and the data driving unit 30 provides data signals to the pixels P.Additional voltage or control signals such as a first power voltageELVDD, a second power voltage ELVSS, an emission control signal EM, andan initialization voltage Vint may be provided to the pixels P under thecontrol of the control unit 40. The control unit 40 may control a timewhen the scan driving unit 20 provides a scan signal to a dummy pixeland may control the data driving unit 30 to provide a data signal thatis the same as the data signal provided or to be provided to a defectivesignal, to the dummy pixel when the scan signal is provided to the dummypixel.

FIGS. 2 through 4 are schematic diagrams of examples of the displaypanel 10 illustrated in FIG. 1 .

Referring to FIGS. 2 through 4 , a plurality of pixels P aligned in amatrix-like shape are formed where a plurality of scan lines SL, aplurality of data lines DL, and a plurality of repair lines RL crosseach other, on a display panel 10a, 10b, or 10c. The pixels P includeemission pixels EP formed on a display area AA and dummy pixels DPformed on a non-display area NA. The non-display area NA may be formedon at least one of top and bottom regions or left and right regions ofthe display area AA. As such, one or more dummy pixels DP may be formedin each pixel column on at least one of top and bottom regions of thepixel column, or one or more dummy pixels DP may be formed in each pixelrow on at least one of left and right regions of the pixel row. Anexample of forming the dummy pixels DP in the pixel column of thenon-display area NA on the top and bottom regions of the display area AAis explained with respect to FIGS. 2 through 4 . This may apply to acase where the dummy pixels DP are formed in the pixel row of thenon-display area NA on the left and right regions of the display areaAA.

Referring to FIG. 2 , the display panel 10a includes a display area AAand a non-display area NA formed below the display area AA. From amongfirst through (n+1)th scan lines SL1 through SLn+1, the first throughnth scan lines SL1 through SLn are formed on the display area AA, andthe (n+1)th scan line SLn+1 is formed on the non-display area NA. Firstthrough mth data lines DL1 through DLm and first through mth repairlines RL1 through RLm are formed separately in pixel columns in thedisplay area M and extending into the non-display area NA. A pluralityof emission pixels EP coupled to the first through nth scan lines SL1through SLn and the first through mth data lines DL1 through DLm areformed in the display area AA, and a plurality of dummy pixels DPcoupled to the (n+1)th scan line SLn+1 and the first through mth datalines DL1 through DLm are formed in the non-display area NA.

Referring to FIG. 3 , the display panel 10b includes a display area AAand a non-display area NA above the display area AA. From among zeroththrough nth scan lines SL0 through SLn, the first through nth scan linesSL1 through SLn are formed on the display area AA, and the zeroth scanline SL0 is formed on the non-display area NA. First through mth datalines DL1 through DLm and first through mth repair lines RL1 through RLmare formed separately in pixel columns in the display area AA andextending into the non-display area NA. A plurality of emission pixelsEP coupled to the first through nth scan lines SL1 through SLn and thefirst through mth data lines DL1 through DLm are formed in the displayarea AA, and a plurality of dummy pixels DP coupled to the zeroth scanline SL0 and the first through mth data lines DL1 through DLm are formedin the non-display area NA.

Referring to FIG. 4 , the display panel 10c includes a display area AAand a non-display area NA formed above and below the display area AA.From among zeroth through (n+1)th scan lines SL0 through SLn+1, thefirst through nth scan lines SL1 through SLn are formed on the displayarea AA, and the zeroth and (n+1)th scan lines SL0 and SLn+1 are formedon the non-display area NA. First through mth data lines DL1 through DLmand first through mth repair lines RL1 through RLm are formed separatelyin pixel columns on the display area AA and the non-display area NA. Aplurality of emission pixels EP coupled to the first through nth scanlines SL1 through SLn and the first through mth data lines DL1 throughDLm are formed on the display area AA, and a plurality of dummy pixelsDP coupled to the zeroth and (n+1)th scan lines SL0 and SLn+1 and thefirst through mth data lines DL1 through DLm are formed on thenon-display area NA.

FIG. 5 is a diagram for describing a method of repairing a defectivepixel by using repair lines of the display panel 10a of FIG. 2 ,according to an embodiment of the present invention.

Referring to FIG. 5 , the emission pixels EP formed in the display areaAA may include pixel circuits PC that are coupled to the first throughnth scan lines SL1 through SLn and the first through mth data lines DL1through DLm, and emission devices E that emit light by receiving adriving current from the pixel circuits PC. The dummy pixels DP formedin the non-display area NA may include only the pixel circuits PC thatare coupled to the (n+1)th scan line SLn+1 and the first through mthdata lines DL1 through DLm.

When an emission pixel EPi coupled to an ith scan line SLi of a firstcolumn is defective, the emission device E of the defective emissionpixel EPi is disconnected from the corresponding pixel circuit PC, andthe disconnected emission device E is coupled to the pixel circuit PC ofthe dummy pixel DP that is coupled to the (n+1)th scan line SLn+1through the repair line RL. The disconnection of the emission device Eand the corresponding pixel circuit PC, the coupling of the repair lineRL and the emission device E, and the coupling of the repair line RL andthe dummy pixel DP may be performed by cutting or shorting byirradiating a laser beam from a substrate side or from an opposite sideof a substrate.

FIGS. 6 and 7 show waveforms of scan signals and data signals providedto the display panel repaired by using the method illustrated in FIG. 5.

Referring to FIG. 6 , the scan driving unit 20 sequentially provides oractivates the first through nth scan signals S1 through Sn to firstthrough nth scan line SL1 through SLn and provides the (n+1)th scansignal Sn+1 to the (n+1)th scan line SLn+1 at the same time as the scansignal Si is provided to the repaired emission pixel EPi.

The data driving unit 30 sequentially provides or activates the firstthrough nth data signals D1 through Dn to the data line DL1 insynchronization with the first through (n+1)th scan signals S1 throughSn+1. In this regard, a data signal Di that is the same as the datasignal Di provided to the defective emission pixel EPi is concurrentlyprovided to the dummy pixel DP. Accordingly, the emission device E ofthe defective emission pixel EPi may receive a current corresponding tothe data signal Di via the pixel circuits PC of the dummy pixels DP andthe repair lines RL1, thereby suppressing or reducing generation of abright spot or a dark spot of the defective emission pixel EPi.

Referring to FIG. 7 , the scan driving unit 20 sequentially provides oractivates the first through (n+1)th scan signals S1 through Sn+1 to thefirst through (n+1)th scan lines SL1 through SLn+1.

The data driving unit 30 sequentially provides or activates the firstthrough nth data signals D1 through Dn to the data line DL1 insynchronization with the first through (n+1)th scan signals S1 throughSn+1. In this regard, a data signal Di that is the same as the datasignal Di provided to the defective emission pixel EPi is again providedto the dummy pixel DP. Accordingly, the emission device E of thedefective emission pixel EPi may receive a current corresponding to thedata signal Di via the pixel circuits PC of the dummy pixels DP and therepair lines RL1, thereby suppressing or reducing generation of a brightspot or a dark spot of the defective emission pixel EPi.

Although a width of the first through (n+1)th scan signals S1 throughSn+1 may be provided as one horizontal period (1H) in FIGS. 6 and 7 , awidth of a scan signal may be provided as two horizontal periods (2H),and widths of adjacent scan signals, for example, widths of the (n−1)thscan signal Sn−1 and the nth scan signal Sn, may be provided to overlapby 1H or less. Accordingly, a lack of charges due to aresistive-capacitive (RC) delay of signal lines caused by a large-sizeddisplay area may be solved or reduced.

FIG. 8 is a diagram for describing a method of repairing a defectivepixel by using the repair lines of the display panel 10b of FIG. 3 ,according to another embodiment of the present invention.

Referring to FIG. 8 , the emission pixels EP formed in the display areaAA may include the pixel circuits PC and the emission devices E thatemit light by receiving a driving current from the pixel circuits PC.The dummy pixels DP formed in the non-display area NA may include onlythe pixel circuits PC.

When the emission pixel EPI coupled to the ith scan line SLi of a firstcolumn is defective, the emission device E of the defective emissionpixel EPi is disconnected from the pixel circuit PC, and thedisconnected emission device E is coupled to the pixel circuit PC of thedummy pixel DP that is coupled to the zeroth scan line SL0 through therepair line RL1. The disconnection of the emission device E and thepixel circuit PC, the coupling of the repair line RL and the emissiondevice E, and the coupling of the repair line RL and the dummy pixel DPmay be performed by cutting or shorting by irradiating a laser beam froma substrate side or from an opposite side of a substrate.

FIGS. 9 and 10 show waveforms of scan signals and data signals providedto the display panel 10b repaired by using the method illustrated inFIG. 8 .

Referring to FIG. 9 , the scan driving unit 20 sequentially provides oractivates the first through nth scan signals S1 through Sn to the firstthrough nth scan line SL1 through SLn and provides the zeroth scansignal S0 to the zeroth scan line S0 at the same time as the scan signalSi is provided to the repaired emission pixel EPi.

The data driving unit 30 sequentially provides or activates the firstthrough nth data signals D1 through Dn to the data line DL1 insynchronization with the zeroth through nth scan signals S0 through Sn.In this regard, the data signal Di that is the same as the data signalDi provided to the defective emission pixel EPi is concurrently providedto the dummy pixel DP. Accordingly, the emission device E of thedefective emission pixel EPi may receive a current corresponding to thedata signal Di via the pixel circuits PC of the dummy pixels DP and therepair lines RL1, thereby suppressing or reducing generation of a brightspot or a dark spot of the defective emission pixel EPi.

Referring to FIG. 10 , the scan driving unit 20 sequentially provides oractivates the zeroth through nth scan signals S0 through Sn to thezeroth through nth scan lines SL0 through SLn.

The data driving unit 30 sequentially provides or activates the firstthrough nth data signals D1 through Dn to the data line DL1 insynchronization with the zeroth through nth scan signals S0 through Sn.In this regard, the data signal Di that is the same as the data signalDi that is to be provided to the defective emission pixel EPi is firstprovided to the dummy pixel DP. Accordingly, the emission device E ofthe defective emission pixel EPi may receive a current corresponding tothe data signal Di via the pixel circuits PC of the dummy pixels DP andthe repair lines RL1, thereby suppressing or reducing generation of abright spot or a dark spot of the defective emission pixel EPi.

Although a width of the zeroth through nth scan signals S0 through Snmay be provided as one horizontal period (1H) in FIGS. 9 and 10 , awidth of a scan signal may be provided as two horizontal periods (2H),and widths of adjacent scan signals, for example, widths of the (n−1)thscan signal Sn−1 and the nth scan signal Sn, may be provided to overlapby 1H or less. Accordingly, a lack of charges due to a RC delay ofsignal lines caused by a large-sized display area may be solved orreduced.

FIG. 11 is a diagram for describing a method of repairing a defectivepixel by using repair lines of the display panel 10C of FIG. 4 ,according to another embodiment of the present invention.

Referring to FIG. 11 , the emission pixels EP formed in the display areaAA may include the pixel circuits PC and the emission devices E thatemit light by receiving a driving current from the pixel circuits PC.The dummy pixels DP formed in the non-display area NA may include onlythe pixel circuits PC.

When the emission pixel EPi coupled to the ith scan line SLi of a firstcolumn and an emission pixel EPp coupled to a pth scan line SLp of thefirst column are defective, the repair line RL1 between the defectiveemission pixels EPi and EPp is disconnected, the emission devices E ofthe defective emission pixels EPi and EPp are disconnected from thepixel circuits PC, and the disconnected emission devices E are coupledto the pixel circuits PC of a first dummy pixel DP1 and a second dummypixie DP2 that are respectively coupled to the zeroth scan line SL0 andthe (n+1)th scan line SLn+1 through the repair lines RL1. Thedisconnection of the emission devices E and the pixel circuits PC, thecoupling of the repair lines RL and the emission devices E, and thecoupling of the repair lines RL and the dummy pixels DP may be performedby cutting or shorting by irradiating a laser beam from a substrate sideor from an opposite side of a substrate.

FIGS. 12 and 13 show waveforms of the scan signals and the data signalsprovided to the display panel 10c repaired by using the methodillustrated in FIG. 11 .

Referring to FIG. 12 , the scan driving unit 20 sequentially provides oractivates the first through nth scan signals S1 through Sn to the firstthrough nth scan line SL1 through SLn and respectively provides thezeroth and (n+1)th scan signals S0 and Sn+1 to the zeroth and (n+1)thscan line SL0 and SLn+1 at the same time as the scan signals Si and Spare respectively provided to the repaired emission pixels EPi and EPp.

The data driving unit 30 sequentially provides or activates the firstthrough nth data signals D1 through Dn to the data line DL1 insynchronization with the zeroth through (n+1)th scan signals S0 throughSn+1. In this regard, the data signals Di and Dp that are the same asthe data signals Di and Dp provided to the defective emission pixels EPiand EPp are concurrently provided to the first and second dummy pixelsDP1 and DP2. Accordingly, the emission devices E of the defectiveemission pixels EPi and EPp may receive current corresponding to thedata signals Di and Dp via the pixel circuits PC of the first and seconddummy pixels DP1 and DP2 and the repair lines RL1, thereby suppressingor reducing generation of a bright spot or a dark spot of the defectiveemission pixels EPi and EPp.

Referring to FIG. 13 , the scan driving unit 20 sequentially provides oractivates the zeroth through (n+1)th scan signals S0 through Sn+1 to thezeroth through (n+1)th scan line SL0 through SLn+1.

The data driving unit 30 sequentially provides or activates the firstthrough nth data signals D1 through Dn to the data line DL1 insynchronization with the zeroth through (n+1)th scan signals S0 throughSn+1. In this regard, the data signal Di that is the same as the datasignal Di that is to be provided to the defective emission pixel EPi isfirst provided to the first dummy pixel DP1. The data signal Dp that isthe same as the data signal Dp provided to the defective emission pixelEPp is again provided to the second dummy pixel DP2. Accordingly, theemission devices E of the defective emission pixels EPi and EPp mayreceive current corresponding to the data signals Di and Dp via thepixel circuits PC of the first and second dummy pixels DP1 and DP2 andthe repair lines RL1, thereby suppressing or reducing generation of abright spot or a dark spot of the defective emission pixels EPi and EPp.

Although a width of the zeroth through (n+1)th scan signals S0 throughSn+1 may be provided as one horizontal period (1H) in FIGS. 12 and 13 ,a width of a scan signal may be provided as two horizontal periods (2H),and widths of adjacent scan signals (for example, widths of the (n−1)thscan signal Sn−1 and the nth scan signal Sn) may be provided to overlapby 1H or less. Accordingly, a lack of charges due to a RC delay ofsignal lines caused by a large-sized display area may be solved.

FIG. 14 is a schematic diagram of the emission pixel EP according to anembodiment of the present invention. FIG. 15 is a plan view of anemission device of the emission pixel EP of FIG. 14 . FIG. 16 is across-sectional view taken along a line A-A′ of FIG. 15 .

Referring to FIG. 14 , the emission pixel EP that is coupled to the scanline SL and the data line DL may include the pixel circuit PC and theemission device E that emits light by receiving a driving current fromthe pixel circuit PC. The pixel circuit PC may include at least one thinfilm transistor (TFT) and at least one capacitor. The emission device Emay be an organic light emitting diode (OLED) including an anode, acathode, and an emission layer formed or located between the anode andthe cathode. The anode of the emission device E may be split orseparated (e.g., physically separated by a gap or space) into at leasttwo anodes so that the emission device E may include at least twosub-emission devices SE1 and SE2.

Referring to FIGS. 15 and 16 , the first sub-emission device SE1includes a first anode AD1, an organic layer OL including an emissionlayer, and a cathode (not shown). The second sub-emission device SE2includes a second anode AD2, the organic layer OL including the emissionlayer, and a cathode. The organic layer OL may be separately or commonlyformed in the first and second sub-emission devices SE1 and SE2. Thecathode may be commonly formed in the first and second sub-emissiondevices SE1 and SE2, and may be formed on an entire surface of asubstrate 101 so that the cathode may be commonly formed in the firstanode AD1 and the second anode AD2 to face each other.

An electrode connection wiring 11 is formed on the substrate 101 and abuffer layer 102. The electrode connection wiring 11 may be formed of aconductive material. For example, the electrode connection wiring 11 maybe formed of amorphous silicon, crystalline silicon, or an oxidesemiconductor. In this case, the electrode connection wiring 11 may beformed on the same layer and of the same material as an active layerincluded in the TFT of the pixel circuit PC. The electrode connectionwiring 11 may be formed of metal. In this case, the electrode connectionwiring 11 may have a single layer structure including metal,semitransparent metal, or a transparent conductive oxide or a threelayer structure including the semitransparent metal and the transparentconductive oxide formed on top and bottom portions of thesemitransparent metal and protecting the semitransparent metal. Thesemitransparent metal may include silver (Ag) or a silver alloy. Thetransparent conductive oxide may include at least one selected from thegroup consisting of indium tin oxide (ITO), indium zinc oxide (IZO),zinc oxide (ZnO), indium oxide (In₂O₃), indium gallium oxide (IGO), andaluminum zinc oxide (AZO). A first insulating film 103 is formed on theelectrode connection wiring 11. A repair connection wiring 13 is formedon the first insulating film 103.

The repair connection wiring 13 may be formed on the same layer and ofthe same material as a conductive electrode included in the TFT of thepixel circuit PC, for example, a gate electrode. A second insulatinglayer 104 is formed on the repair connection wiring 13. In a firstconnection unit CU1, a first contact metal CM1 and a second contactmetal CM2 formed on the second insulating layer 104 are coupled to theelectrode connection wiring 11 through contact holes. A circuitconnection wiring 12, that is coupled to a circuit wiring 15 coupled tothe pixel circuit PC, is coupled to the electrode connection wiring 11through a contact hole, in a second connection unit CU2. The circuitwiring 15, along with the active layer included in the TFT of the pixelcircuit PC, may be formed of amorphous silicon, crystalline silicon, oran oxide semiconductor or may be formed on the same layer and of thesame material as a source electrode and a drain electrode that areincluded in the TFT. The circuit connection wiring 12 is coupled to theelectrode connection wiring 11 between the first connection units CU1 sothat a first cut node CN1 and a second cut node CN2 are formed in theelectrode connection wiring 11. A short wiring 14 extending from thefirst contact metal CM1 overlaps with a part of the repair connectionwiring 13 in a first short node SN1 and is provisionally coupled to therepair connection wiring 13. The repair line RL is coupled to the repairconnection wiring 13 through a contact hole. The repair line RL, thecircuit connection wiring 12, the first and second contact metals CM1and CM2, and the short wiring 14 may be formed on the same layer and ofthe same material as a conductive electrode included in the TFT of thepixel circuit PC, for example, the source electrode and the drainelectrode. A third insulating layer 105 is formed on the repair line RL,the first and second contact metals CM1 and CM2, and the short wiring14. The first anode AD1 and the second anode AD2 are formed on the thirdinsulating layer 105.

A first protrusion unit AD1′ extending from the first anode AD1 iscoupled to the electrode connection wiring 11 through the first contactmeal CM1 in the first connection unit CU1. A second protrusion unit AD2′extending from the second anode AD2 is coupled to the electrodeconnection wiring 11 through the second contact meal CM2 in the firstconnection unit CU1. Accordingly, the first anode AD1 and the secondanode AD2 are electrically coupled to each other by the electrodeconnection wiring 11. A fourth insulating layer 106 that covers edges ofthe first anode AD1 and the second anode AD2 is formed on the firstanode AD1 and the second anode AD2.

FIG. 17 is a schematic diagram of the dummy pixel DP according to anembodiment of the present invention. FIG. 18 is a plan view of a part ofthe dummy pixel DP of FIG. 17 . FIG. 19 is a cross-sectional view takenalong a line B-B′ of FIG. 18 .

Referring to FIG. 17 , the dummy pixel DP that is coupled to the zerothscan line SL0 and/or the (n+1)th scan line SLn+1 and the data line DLmay include only the pixel circuit PC. The pixel circuit PC of the dummypixel DP may be the same (e.g., the same design, structure, and/orfunction) as the pixel circuit PC of the emission pixel EP.

Referring to FIGS. 18 and 19 , a power connection wiring 18 is formed onthe substrate 101 and the buffer layer 102. The power connection wiring18 may be formed of amorphous silicon, crystalline silicon, or an oxidesemiconductor. The power connection wiring 18 may be formed on the samelayer and of the same material as an active layer included in the TFT ofthe pixel circuit PC. The first insulating layer 103 is formed on thepower connection wiring 18. A repair connection wiring 16 is formed onthe first insulating layer 103.

The repair connection wiring 16 may be formed on the same layer and ofthe same material as a conductive electrode included in a TFT of thepixel circuit PC, for example, a gate electrode. The second insulatinglayer 104 is formed on the repair connection wiring 16. On the secondinsulating layer 104, a short wiring 17 coupled to the pixel circuit PCoverlaps with a part of the repair connection wiring 16 in the firstshort node SN2 and is provisionally coupled to the repair connectionwiring 16. The repair line RL is coupled to the repair connection wiring16 through a contact hole. The repair line RL and a power voltage lineELVDDL in a boundary of the display panel 10 are coupled to the powerconnection wiring 18 so that the repair line RL and the power voltageline ELVDDL are electrically coupled to each other. When the repair lineRL is used to repair the emission pixel EP, the power voltage lineELVDDL is disconnected from the repair line RL by cutting the powerconnection wiring 18.

The repair line RL, the short wiring 17, and the power voltage lineELVDDL may be formed on the same layer and of the same material as aconductive electrode included in the TFT of the pixel circuit PC, forexample, a source electrode and a drain electrode. The third insulatinglayer 105 and the fourth insulating layer 106 are sequentially formed onthe repair line RL, the short wiring 17, and the power voltage lineELVDDL.

FIG. 20 is a flowchart for explaining a method of repairing a defectivepixel, according to an embodiment of the present invention.

Referring to FIG. 20 , after the display panel 10 is manufactured, thedefective pixel of the display area AA is detected through a panel testperformed on the display panel 10 (operation S21). The panel test mayinclude, for example, a lighting test, an aging test, etc. The defectivepixel is an emission pixel recognized as a bright spot or a dark spot.The bright spot or the dark spot may be generated due to a defectivepixel circuit or a defective emission device. When an anode and acathode of an emission device are shorted due to a defect presenttherebetween, and when a value of a resistance Rdef formed in parallelwith the anode and the cathode is small, a driving current generated inthe pixel circuit PC flows from the anode to the cathode through theresistance Rdef, and thus a voltage of the anode is not sufficientlyhigher than a turn-on voltage of the emission device, which causes thedark spot in which the emission device does not emit light.

A pixel that is visibly recognized as a bright spot or a dark spot ofthe display panel 10 may be detected through an optical microscope of alighting inspection apparatus.

In a case of a visible defect in which a sub-emission device that is thebright spot or the dark spot is visibly recognized among a plurality ofsub-emission devices, the sub-emission device having the defect of thebright spot or the dark spot is separated or electrically isolated fromthe pixel circuit PC (operation S22).

In a case of an invisible defect in which a defective sub-emissiondevice is not visibly recognized among a plurality of sub-emissiondevices, an emission device of the defective pixel is coupled to therepair line RL and the pixel circuit PC of the dummy pixel DP is coupledto the repair line RL so that the defective pixel is coupled to thedummy pixel DP (operation S23). It is determined whether the defectivepixel normally emits light (operation S24).

When the defective pixel normally emits light by the coupling of thedefective pixel and the dummy pixel DP, the defective pixel isdetermined to have resulted from the defective pixel circuit. Thus, inorder to completely insulate the defective pixel circuit from theemission device, the pixel circuit PC of the defective pixel may beselectively separated or electrically isolated from the emission device(operation S25). Operation S25 may be selectively performed.

When the defective pixel does not normally emit light by the coupling ofthe defective pixel and the dummy pixel DP, the defective pixel isdetermined to have resulted from the short defect of the emissiondevice, and the sub-emission devices are disconnected from each other(operation S26).

FIGS. 21 through 26 are diagrams for explaining a method of repairing adefective pixel (operation S22) in a case of a visible defect of FIG. 20, according to embodiments of the present invention.

The repairing method of FIGS. 21 through 26 describes an example of thedummy pixel DP coupled to the (n+1)th scan line SLn+1 among the firstthrough (n+1)th scan lines SL1 through SLn+1 like the display panel 10aof FIG. 2 . This may apply to the display panels 10b and 10c of FIGS. 3and 4 .

Referring to FIGS. 21 through 23 , when the first sub-emission deviceSE1 of the defective emission pixel ER is visibly recognized to have ashort defect, the first sub-emission device SE1 is disconnected from thesecond sub-emission device SE2. In this regard, the first cut node CN1of the electrode connection wiring 11 is cut by irradiating a laserbeam. Accordingly, the first sub-emission device SE1 becomes a dark spotand a driving current flows from an emission pixel circuit PCi to thesecond sub-emission device SE2 so that the second sub-emission deviceSE2 may emit light without any perceivable brightness reduction.

Referring to FIGS. 24 through 26 , when the second sub-emission deviceSE2 of the defective emission pixel EPi is visibly recognized to have ashort defect, the second sub-emission device SE2 is disconnected fromthe first sub-emission device SE1. In this regard, the second cut nodeCN2 of the electrode connection wiring 11 is cut by irradiating thelaser beam. Accordingly, the second sub-emission device SE2 becomes thedark spot, and the driving current flows from the emission pixel circuitPCi to the first sub-emission device SE1 so that the first sub-emissiondevice SE1 may emit light without any perceivable brightness reduction.

In the embodiments described with reference to FIGS. 21 through 26 , theemission pixel EPi has a short defect, and the emission pixel circuitPCi is normal, and thus the emission pixel EPi is not necessarilycoupled to the dummy pixel DP through the repair line RL.

FIGS. 27 through 29B are diagrams for explaining a method of repairing adefective pixel (operations S23 and S25) in the case of an invisibledefect of FIG. 20 , according to embodiments of the present invention.

The repairing method of FIGS. 27 through 29B describes an example of thedummy pixel DP coupled to the (n+1)th scan line SLn+1 among the firstthrough (n+1)th scan lines SL1 through SLn+1 like the display panel 10aof FIG. 2 . This may apply to the display panels 10b and 10c of FIGS. 3and 4 .

Referring to FIGS. 27 through 29B, although the emission pixel EPicoupled to the ith scan line SLi is determined to be defective, when itis not determined whether the defective emission pixel EPi has resultedfrom a defective pixel circuit or a defective emission device, theprovisionally coupled repair connection wiring 13 and the short wiring14 are shorted by irradiating a laser beam onto the first short nodeSN1, and then the provisionally coupled repair connection wiring 16 andthe short wiring 17 are shorted by irradiating the laser beam onto thesecond short node SN2, and thus the emission pixel EPi and the dummypixel DP are electrically coupled to each other (operation S23). Thepower voltage line ELVDDL and the repair line RL are disconnected fromeach other by irradiating the laser beam onto the power connectionwiring 18.

After the coupling of the repair line RL and the dummy pixel DP anddefective emission pixel EPi, when the first sub-emission device SE1 andthe second sub-emission device SE2 normally emit light, because thedefective emission pixel EPi is determined to have resulted from thedefective emission pixel circuit PCi, to completely insulate thedefective emission pixel circuit PCi from the defective emission pixelEPi, the circuit connection wiring 12 and the circuit wiring 15 areseparated or electrically isolated from each other by cutting thecircuit wiring 15 by irradiating the laser beam onto the circuit wiring15, and thus the emission pixel circuit PCi is separated or electricallyisolated from the emission pixel EPi (operation S25).

Accordingly, a driving current flows from a dummy pixel circuit PCn+1 tothe first sub-emission device SE1 and the second sub-emission device SEso that the emission pixel EPi may emit light without any perceivablebrightness reduction.

FIGS. 30A through 32 are diagrams for explaining a method of repairing adefective pixel (operations S23 and S26) in the case of the invisibledefect of FIG. 20 , according to embodiments of the present invention.

The repairing method of FIGS. 30A through 32 describes an example of thedummy pixel DP coupled to the (n+1)th scan line SLn+1 among the firstthrough (n+1)th scan lines SL1 through SLn+1 like the display panel 10aof FIG. 2 . This may apply to the display panels 10b and 10c of FIGS. 3and 4 .

Referring to FIGS. 28B and 30A through 32 , although the emission pixelEPi coupled to the ith scan line SL1 is determined to be defective, whenit is not determined whether the defective emission pixel EPI hasresulted from a defective pixel circuit or a defective emission device,the provisionally coupled repair connection wiring 13 and the shortwiring 14 are shorted by irradiating a laser beam onto the first shortnode SN1, and the provisionally coupled repair connection wiring 16 andthe short wiring 17 are shorted by irradiating the laser beam onto thesecond short node SN2, and thus the emission pixel EPi and the dummypixel DP are electrically coupled to each other (operation S23). Thepower voltage line ELVDDL and the repair line RL are disconnected fromeach other by irradiating the laser beam onto the power connectionwiring 18.

After the coupling of the repair line RL, the dummy pixel DP, and theemission pixel EPi, when the first sub-emission device SE1 and thesecond sub-emission device SE2 do not normally emit light, because thedefective emission pixel EPi is determined to have resulted from thedefective emission device E, the first cut node CN1 of the electrodeconnection wiring 11 is cut by irradiating the laser beam onto theelectrode connection wiring 11 (operation S26). Thus, the firstsub-emission device SE1 and the second sub-emission device SE2 areseparated or electrically isolated from each other, the firstsub-emission device SE1 receives a driving current from the dummy pixelcircuit PCn+1, and the second sub-emission device SE2 receives a drivingcurrent from the emission pixel circuit PCi.

If the defective emission pixel EPi is determined to have resulted froma short defect of the first sub-emission device SE1, as shown in FIG.30A, the first sub-emission device SE1 becomes a dark spot, and thesecond sub-emission device SE2 may emit light by the driving currentfrom the emission pixel circuit PCi without any perceivable brightnessreduction.

If the defective emission pixel EPi is determined to have resulted froma short defect of the second sub-emission device SE2, as shown in FIG.30B, the second sub-emission device SE2 becomes the dark spot, and thefirst sub-emission device SE1 may emit light by the driving current fromthe dummy pixel circuit PCn+1 without any perceivable brightnessreduction.

FIG. 33 is a circuit diagram of an emission pixel EP1 according to anembodiment of the present invention.

Referring to FIG. 33 , the emission pixel EP1 includes the emissiondevice E and a pixel circuit 2A for supplying a current to the emissiondevice E. The dummy pixel DP includes the pixel circuit 2A excluding theemission device E. The emission device E includes an anode, a cathode,and an emission layer formed or located between the anode and thecathode, and may be an OLED having a structure in which the anode issplit or separated into a plurality of anodes. The emission device E mayinclude first through nth OLEDs OLED1 through OLEDn that are coupled inparallel to each other by the plurality of anodes resulting from thesplitting of the anode. Accordingly, a driving current of the pixelcircuit 2A is separately provided to the first through nth OLEDs OLED1through OLEDn. If a defective OLED is separated or electrically isolatedfrom the corresponding pixel circuit, because the driving current isseparately provided to the other OLEDs, the OLEDs may emit light withoutany perceivable brightness loss. The circuit connection wiring 12coupled to the emission device E is disconnected from the circuit wiring15 coupled to the pixel circuit 2A by cutting the circuit wiring 15, andthus the pixel circuit 2A and the emission device E may be separated orelectrically isolated from each other.

The pixel circuit 2A may include first through fourth transistors TA1through TA4, and first and second capacitors C1 and C2.

A gate electrode of the first transistor TA1 receives a scan signal Sfrom a scan line. A first electrode of the first transistor TA1 receivesa data signal D from a data line. A second electrode of the firsttransistor TA1 is coupled to a first node N1.

A gate electrode of the second transistor TA2 is coupled to a secondnode N2. A first electrode of the second transistor TA2 receives a firstpower voltage ELVDD from a first power source. A second electrode of thesecond transistor TA2 is coupled to the anode of the OLED. The secondtransistor TA2 functions as a driving transistor.

The first capacitor C1 is coupled between the first node N1, and thesecond electrode of the second transistor TA2 and the first powersource. The second capacitor C2 is coupled between the first node N1 andthe second node N2.

A gate electrode of the third transistor TA3 receives a first controlsignal GC. A first electrode of the third transistor TA3 is coupled tothe gate electrode of the second transistor TA2. A second electrode ofthe third transistor TA3 is coupled to the anode of the OLED and thesecond electrode of the second transistor TA2.

A gate electrode of the fourth transistor TA4 receives a second controlsignal SUS_ENB. A first electrode of the fourth transistor TA4 receivesan auxiliary voltage Vsus. A second electrode of the fourth transistorTA4 is coupled to the data line and receives the data signal D.

In an initialization period, the scan signal S having a low level isprovided to the scan line, and a second control signal SUS_ENB having alow level is provided to the gate electrode of the fourth transistorTA4. In this case, the data line is in a high impedance (Hi-Z) state. Assuch, the first transistor TA1 and the fourth transistor TA4 are turnedon and thus the auxiliary voltage Vsus having a high level is providedto the first node N1, a voltage of the second node N2 is reduced, andthe second node N2 is maintained at an initialization voltage (e.g., apredetermined initialization voltage).

In a compensation period, the auxiliary voltage Vsus having a high levelis provided to the first node N1 through the data line. The firstcontrol signal GC is provided at a low level and thus the thirdtransistor TA3 is turned on. As such, the second transistor TA2 isdiode-connected and thus a current flows until a voltage correspondingto a threshold voltage of the second transistor TA2 is stored in thesecond capacitor C2. After that, the second transistor TA2 is turnedoff.

In a scan/data input period, the scan signal S having a low level isprovided to the scan line and thus the first transistor TA1 is turnedon, and the data signal D is provided through the data line. As such, avoltage difference between the driving voltage ELVDD and a voltage ofthe first node N1 is stored in the first capacitor C1.

In an emission period, the first power voltage ELVDD is provided at ahigh level, and the second power voltage ELVSS is provided at a lowlevel. A current path from the first power voltage ELVDD to the cathodeof the OLED is formed via the second transistor TA2, and the emissiondevices E of all the emission pixels EP1 emit light at a brightnesscorresponding to the data signal.

FIG. 34 is a circuit diagram of an emission pixel EP2 according toanother embodiment of the present invention.

Referring to FIG. 34 , the emission pixel EP2 includes the emissiondevice E and a pixel circuit 2B for supplying a current to the emissiondevice E. The dummy pixel DP includes the pixel circuit 2B excluding theemission device E. The emission device E includes an anode, a cathode,and an emission layer formed or located between the anode and thecathode, and may be an OLED having a structure in which the anode issplit or physically separated into a plurality of anodes having a gap orspace between the separated anodes. The emission device E may includethe first through nth OLEDs OLED1 through OLEDn that are coupled inparallel to each other through the plurality of anodes resulting fromthe splitting of the anode. Accordingly, a driving current of the pixelcircuit 2B is separately provided to the first through nth OLEDs OLED1through OLEDn. If a defective OLED is separated or electricallyisolated, because the driving current is separately provided to theother OLEDs, the OLEDs may emit light without any perceivable brightnessloss. The circuit connection wiring 12 coupled to the emission device Eis disconnected from the circuit wiring 15 coupled to the pixel circuit2B by cutting the circuit wiring 15, and thus the pixel circuit 2B andthe emission device E may be separated or electrically isolated fromeach other.

The pixel circuit 2B includes first through fifth transistors TB1through TB5, and first through third capacitors C1 through C3.

A gate electrode of the first transistor TB1 receives the scan signal Sfrom a scan line. A first electrode of the first transistor TB1 iscoupled to a data line and receives the data signal D from the dataline. A second electrode of the first transistor TB1 is coupled to thefirst node N1.

A gate electrode of the second transistor TB2 receives a first controlsignal GW. A first electrode of the second transistor TB2 is coupled tothe first node N1. A second electrode of the second transistor TB2 iscoupled to the second node N2.

A gate electrode of the third transistor TB3 is coupled to a third nodeN3. A first electrode of the third transistor TB3 receives a first powervoltage ELVDD from a first power source. A second electrode of the thirdtransistor TB3 is coupled to the anode of the OLED. The third transistorTB3 functions as a driving transistor.

A gate electrode of the fourth transistor TB4 receives a second controlsignal GC. A first electrode of the fourth transistor TB4 is coupled tothe third node N3 and the gate electrode of the third transistor TB3. Asecond electrode of the fourth transistor TB4 is coupled to the anode ofthe OLED.

A gate electrode of the fifth transistor TB5 receives the second controlsignal GC. A first electrode of the fifth transistor TB5 is coupled tothe data line and receives the data signal D from the data line. Asecond electrode of the fifth transistor TB5 is coupled to the secondnode N2.

The first capacitor C1 is coupled between the first node N1 and the gateelectrode of the fifth transistor TB5. The second capacitor C2 iscoupled between the second node N2 and the first power source providingthe first power voltage ELVDD. The third capacitor C3 is coupled betweenthe second node N2, and the third node N3, and the gate electrode of thethird transistor TB3. When the first transistor TB1 is turned on, thefirst capacitor C1 is charged with a voltage corresponding to the datasignal D provided from the data line.

In an initialization period, the first power voltage ELVDD and thesecond control signal GC are provided at a low level. The data line isin a high impedance (Hi-Z) state. As such, the fifth transistor TB5 andthe fourth transistor TB4 are sequentially turned on and thus the thirdtransistor TB3 is diode-connected, and a voltage of the anode of theOLED and a voltage of the third node N3 are initialized to a level ofthe driving voltage ELVDD.

In a compensation period, the second control signal GC is provided at alow level, and an auxiliary voltage Vsus having a high level is providedto the data line. As such, the fifth transistor TB5 is turned on andthus the auxiliary voltage Vsus is provided to the second node N2. Also,the fourth transistor TB4 is turned on and thus the third transistor TB3is diode-connected, and a current flows until a voltage corresponding toa threshold voltage of the third transistor TB3 is stored in the thirdcapacitor C3. Thereafter, the third transistor TB3 is turned off.

In a data transmission period, the first power voltage ELVDD and thesecond power voltage ELVSS are provided at a high level, and the firstcontrol signal GW is provided at a low level. As such, the secondtransistor TB2 is turned on and thus the data signal D written in theemission pixel EP2 in a scan period of an (N−1)th frame stored in thefirst capacitor C1 moves to the second node N2. Accordingly, a voltagedifference between the driving voltage ELVDD and a voltage of the secondnode N2 is stored in the second capacitor C2.

In a scan/emission period Scan/Emission, a scan period and an emissionperiod are concurrently (e.g., simultaneously) performed. In thescan/emission period Scan/Emission, the first power voltage ELVDD isprovided at a high level, and the second power voltage ELVSS is providedat a low level. Also, the scan signal S at a low level is input to thescan line and thus the first transistor TB1 is turned on, and a datasignal is input to the emission pixel EP2 coupled to the scan line. Assuch, a voltage corresponding to a data signal of an Nth frame is storedin the first capacitor C1.

The second transistor TB2 is turned off to block the first node N1 andthe second node N2. Also, a current path from the first power voltageELVDD to the cathode of the OLED is formed via the turned-on thirdtransistor TB3, and the OLED emits light to a brightness correspondingto the data signal written in the emission pixel EP2 in the scan periodof the (N−1)th frame stored in the second capacitor C2. In this regard,all emission pixels EP2 in the display area AA concurrently (e.g.,simultaneously) emit light. That is, in the scan/emission periodScan/Emission, data signals of the Nth frame are sequentially inputaccording to scan signals and, at the same time, all emission pixels EP2in the display area AA concurrently (e.g., simultaneously) emit light incorrespondence with data signals of the (N−1)th frame.

FIG. 35 is a circuit diagram of an emission pixel EP3 according toanother embodiment of the present invention.

Referring to FIG. 35 , the emission pixel EP3 includes the emissiondevice E and a pixel circuit 2C for supplying a current to the emissiondevice E. The dummy pixel DP includes the pixel circuit 2C excluding theemission device E. The emission device E includes an anode, a cathode,and an emission layer formed or located between the anode and thecathode, and may be an OLED having a structure in which the anode issplit into a plurality of anodes. The emission device E may include thefirst through nth OLEDs OLED1 through OLEDn that are coupled in parallelto each other according to the plurality of anodes resulting from thesplitting of the anode. Accordingly, a driving current of the pixelcircuit 2B is separately provided to the first through nth OLEDs OLED1through OLEDn. If a defective OLED is separated or electrically isolatedfrom the corresponding pixel circuit, because the driving current isseparately provided to the other OLEDs, the OLEDs may emit light withoutany perceivable brightness loss. The circuit connection wiring 12coupled to the emission device E is disconnected from the circuit wiring15 coupled to the pixel circuit 2C by cutting the circuit wiring 15, andthus the pixel circuit 2C and the emission device E may be separated orelectrically isolated from each other.

The pixel circuit 2C includes first through eighth transistors TC1through TC8, and the first and second capacitors C1 and C2.

A gate electrode of the first transistor TC1 receives the scan signal Sfrom a scan line. A first electrode of the first transistor TC1 iscoupled to a data line and receives a data signal D from the data line.A second electrode of the first transistor TC1 is coupled to the firstnode N1.

A gate electrode of the second transistor TC2 receives the first controlsignal GW. A first electrode of the second transistor TC2 is coupled tothe first node N1. A second electrode of the second transistor TC2 iscoupled to the second node N2.

A gate electrode of the third transistor TC3 receives a second controlsignal GI. A first electrode of the third transistor TC3 is coupled toan initialization power source and receives an initialization voltageVint from the initialization power source. A second electrode of thethird transistor TC3 is coupled to the third node N3.

A gate electrode of the fourth transistor TC4 receives the first controlsignal GW. A first electrode of the fourth transistor TC4 is coupled tothe third node N3. A second electrode of the fourth transistor TC4 iscoupled to a fourth node N4.

A gate electrode of the fifth transistor TC5 receives the second controlsignal GI. A first electrode of the fifth transistor TC5 is coupled to afirst power source and receives the first power voltage ELVDD from thefirst power source. A second electrode of the fifth transistor TC5 iscoupled to the second node N2.

A gate electrode of the sixth transistor TC6 is coupled to the thirdnode N3. A first electrode of the sixth transistor TC6 is coupled to thesecond node N2. A second electrode of the sixth transistor TC6 iscoupled to the fourth node N4. The sixth transistor TC6 functions as adriving transistor.

A gate electrode of the seventh transistor TC7 receives a third controlsignal GE. A first electrode of the seventh transistor TC7 is coupled tothe fourth node N4. A second electrode of the seventh transistor TC7 iscoupled to the anode of the OLED.

A gate electrode of the eighth transistor TC8 receives the third controlsignal GE. A first electrode of the eighth transistor TC8 is coupled tothe first power source and receives the first power voltage ELVDD fromthe first power source. A second electrode of the eighth transistor TC8is coupled to the second node N2.

The first capacitor C1 is coupled between the first node N1 and a thirdpower source for providing a third power voltage Vhold. When the firsttransistor TC1 is turned on, the first capacitor C1 is charged with avoltage corresponding to the data signal D provided from the data line.The third power source may be set as a power source fixed to a voltage(e.g., a predetermined voltage, for example, a direct current (DC) powersource). For example, the third power source may be set as the firstpower source for providing the first power voltage ELVDD or theinitialization power source for providing the initialization voltageVint. The second capacitor C2 is coupled between the third node N3 andthe first power source.

In an initialization period, the first power voltage ELVDD is providedat a high level, and the second power voltage ELVSS and the secondcontrol signal GI are provided at a low level. As such, the thirdtransistor TC3 and the fifth transistor TC5 are turned on, and thus thefirst power voltage ELVDD is provided to the second node N2 and theinitialization voltage Vint is provided to the third node N3.

In a compensation/data transmission period, the first power voltageELVDD, the second power voltage ELVSS, and the first control signal GWare provided at a low level. As such, the second transistor TC2 isturned on, and thus the data signal D, written in the emission pixel EP3in a scan period of an (N−1)th frame stored in the first capacitor C1,moves to the second node N2. Also, the fourth transistor TC4 is turnedon and thus the sixth transistor TC6 is diode-connected, and a currentflows through the diode-connected sixth transistor TC6, and thus athreshold voltage of the sixth transistor TC6 is compensated, and avoltage difference between the driving voltage ELVDD and a voltage ofthe second node N2 is stored in the second capacitor C2.

In a scan/emission period, a scan period and an emission period areconcurrently (e.g., simultaneously) performed. In the scan/emissionperiod, the first power voltage ELVDD is provided at a high level, andthe second power voltage ELVSS and the third control signal GE areprovided at a low level. Also, the scan signal S having a low level isinput to the scan line and thus the first transistor TC1 is turned on,and a data signal of an Nth frame is input to the emission pixels EP3coupled to the scan line. As such, a voltage corresponding to the datasignal of the Nth frame is stored in the first capacitor C1.

The second transistor TC2 is turned off to block the first node N1 andthe second node N2. Also, the seventh and eighth transistors TC7 and TC8are turned on and thus a current path from the first power voltage ELVDDto the cathode of the OLED is formed via the turned-on sixth transistorTC6, and the OLED emits light at a brightness corresponding to a datasignal written in the emission pixel EP3 in the scan period of the(N−1)th frame stored in the second capacitor C2. In this regard, allemission pixels EP3 in the display area AA concurrently (e.g.,simultaneously) emit light. That is, in the scan/emission period, datasignals of the Nth frame are sequentially input according to scansignals and, at the same time, all emission pixels EP3 in the displayarea AA concurrently (e.g., simultaneously) emit light in correspondencewith data signals of the (N−1)th frame. The emission period maypartially overlap with the scan period and may be shorter than the scanperiod.

FIG. 36 is a circuit diagram of an emission pixel EP4 according toanother embodiment of the present invention.

Referring to FIG. 36 , the emission pixel EP4 includes the emissiondevice E and a pixel circuit 2D for supplying a current to the emissiondevice E. The dummy pixel DP includes the pixel circuit 2D excluding theemission device E. The emission device E includes an anode, a cathode,and an emission layer formed or located between the anode and thecathode, and may be an OLED having a structure in which the anode issplit into a plurality of anodes. The emission device E may include thefirst through nth OLEDs OLED1 through OLEDn that are coupled in parallelto each other according to the plurality of anodes resulting from thesplitting of the anode. Accordingly, a driving current of the pixelcircuit 2D is separately provided to the first through nth OLEDs OLED1through OLEDn. If a defective OLED is separated or electricallyisolated, because the driving current is separately provided to theother OLEDs, the OLEDs may emit light without any perceivable brightnessloss. The circuit connection wiring 12 coupled to the emission device Eis disconnected from the circuit wiring 15 coupled to the pixel circuit2D by cutting the circuit wiring 15, and thus the pixel circuit 2D andthe emission device E may be separated or electrically isolated fromeach other.

The pixel circuit 2D includes first and second transistors TD1 and TD2,and a first capacitor C.

A gate electrode of the first transistor TD1 is coupled to a scan line.A first electrode of the first transistor TD1 is coupled to a data line.A second electrode of the first transistor TD1 is coupled to the firstnode N1.

A gate electrode of the second transistor TD2 is coupled to the firstnode N1. A first electrode of the second transistor TD2 receives thefirst power voltage ELVDD from a first power source. A second electrodeof the second transistor TD2 is coupled to the anode of the OLED.

A first electrode of the capacitor C is coupled between the first nodeN1. A second electrode of the capacitor C receives (e.g., is coupled to)the first power voltage ELVDD from the first power source.

When the scan signal S is provided from the scan line, the firsttransistor TD1 transfers the data signal D provided from the data lineto the first electrode of the capacitor C. As such, a voltagecorresponding to the data signal D is charged in the capacitor C, and adriving current corresponding to the voltage charged in the capacitor Cis transferred to the emission device E through the second transistorTD2, and thus the emission device E emits light.

Although the emission pixel EP4 of FIG. 36 has a 2Tr-1Cap structureincluding two transistors and one capacitor in one pixel, the presentinvention is not limited thereto. That is, the emission pixel EP4 mayhave various structures including two or more transistors and one ormore capacitors by forming additional wirings or omitting the existingwirings.

FIG. 37 is a schematic diagram of a display panel 10d according toanother embodiment of the present invention.

Referring to FIG. 37 , a plurality of pixels P aligned in a matrix-likeshape where the plurality of scan lines SL, the plurality of data linesDL, and the plurality of repair lines RL cross each other are formed onthe display panel 10d. The pixels P include emission pixels EP formed onthe display area AA, and dummy pixels DP formed on the non-display areaNA. The non-display area NA may be formed on at least one of top andbottom regions of the display area AA. As such, one or more dummy pixelsDP may be formed in each pixel column on at least one of top and bottomregions of the pixel column. FIG. 37 shows an example that the dummypixel DP is formed on the bottom region of the pixel column.

One emission pixel EP includes first through third sub-emission pixelsSEP1, SEP2, and SEP3 aligned in a column direction. Each of the firstthrough third sub-emission pixels SEP1, SEP2, and SEP3 includes thepixel circuit PC, and the emission device E coupled to the pixel circuitPC. The emission device E may be an OLED including an anode, a cathode,and an emission layer between the anode and the cathode. The anode ofthe emission device E may be split into at least two anodes and thus theemission device E may include at least two sub-emission devices.

The pixel circuits PC and/or the emission devices E of the first throughthird sub-emission pixels SEP1, SEP2, and SEP3 may differ in size. Thefirst through third sub-emission pixels SEP1, SEP2, and SEP3 arecommonly coupled to one scan line, for example, an ith scan line SLi,and are respectively coupled to first through third data lines DLj_1,DLj_2, and DLj_3. Accordingly, if a scan signal is provided to the ithscan line SLi, data signals are provided via the first through thirddata lines DLj_1, DLj_2, and DLj_3 respectively to the first throughthird sub-emission pixels SEP1, SEP2, and SEP3, and thus each of thefirst through third sub-emission pixels SEP1, SEP2, and SEP3 is chargedwith a voltage corresponding to the provided data signal and emits lightat a brightness corresponding to the charged voltage.

The dummy pixel DP includes first through third sub-dummy pixels SDP1,SDP2, and SDP3 aligned in a column direction. Each of the first throughthird sub-dummy pixels SDP1, SDP2, and SDP3 includes only a pixelcircuit PC excluding an emission device E. The pixel circuit PC of eachof the first through third sub dummy pixels SDP1, SDP2, and SDP3 mayhave the same or substantially the same design and function as the pixelcircuit PC of each of the first through third sub-emission pixels SEP1,SEP2, and SEP3. The first through third sub-dummy pixels SDP1, SDP2, andSDP3 are commonly coupled to one scan line, for example, an (n+1)th scanline SLn+1, and are respectively coupled to the first through third datalines DLj_1, DLj_2, and DLj_3. Accordingly, if a scan signal is providedto the (n+1)th scan line SLn+1, data signals are provided via the firstthrough third data lines DLj_1, DLj_2, and DLj_3 respectively to thefirst through third sub-dummy pixels SDP1, SDP2, and SDP3.

From among the first through third sub-emission pixels SEP1, SEP2, andSEP3, if the pixel circuit PC of the second sub-emission pixel SEP2 isdefective, the pixel circuit PC of the second sub-emission pixel SEP2 isseparated or electrically isolated from the second sub-emission deviceSE2, and the second sub-emission device SE2 is coupled to the repairline RLj. Also, from among the first through third sub-dummy pixelsSDP1, SDP2, and SDP3, the pixel circuit PC of the second sub-dummy pixelSDP2 corresponding to the second sub-emission pixel SEP2 is coupled tothe repair line RLj.

FIG. 37 shows an example that a dummy pixel is formed as a plurality ofsub-pixels when a plurality of sub-pixels included in one pixel havedifferent characteristics. However, even in this case, the same drivingprincipal may also be applied by forming a dummy pixel as one sub-pixeland correcting a gamma value of a data signal provided to the dummypixel.

FIG. 38 is a circuit diagram of an emission pixel EP5 according toanother embodiment of the present invention.

Referring to FIG. 38 , the emission pixel EP5 includes the emissiondevice E and a pixel circuit 2E for supplying a current to the emissiondevice E. The dummy pixel DP includes the pixel circuit 2E excluding theemission device E. The emission device E includes an anode, a cathode,and an emission layer formed or located between the anode and thecathode, and may be an OLED having a structure in which the anode issplit into a plurality of anodes. The emission device E may include thefirst through nth OLEDs OLED1 through OLEDn that are coupled in parallelto each other through the plurality of anodes resulting from thesplitting of the anode. Accordingly, a driving current of the pixelcircuit 2E is separately provided to the first through nth OLEDs OLED1through OLEDn. If a defective OLED is separated or electrically isolatedfrom the corresponding pixel circuit, because the driving current isseparately provided to the other OLEDs, the OLEDs may emit light withoutany perceivable brightness loss. The circuit connection wiring 12coupled to the emission device E is disconnected from the circuitwirings 15 and 19 coupled to the pixel circuit 2E by cutting the circuitwirings 15 and 19, and thus the pixel circuit 2E and the emission deviceE may be separated or electrically isolated from each other.

The pixel circuit 2E of FIG. 38 which further includes a ninthtransistor TC9 and accordingly further includes the circuit wiring 19coupled to the emission device E is the same as the pixel circuit 2C ofFIG. 35 in terms of structure and operation, and thus a detaileddescription thereof will be omitted here.

A gate electrode of the ninth transistor TC9 receives the second controlsignal GI. A first electrode of the ninth transistor TC9 is coupled toan initialization power line and receives the initialization voltageVint from the initialization power line. A second electrode of the ninthtransistor TC9 is coupled to the anode of the emission device E. Theninth transistor TC9 is turned on by the second control signal GI andprovides the initialization voltage Vint to the anode.

FIG. 39 is a plan view of the emission pixel EP including the pixelcircuit 2E of FIG. 38 .

FIG. 39 shows the emission pixel EP including three emission sub-pixelsSEP_R, SEP_G, and SEP_B that are coupled to the scan line SL and aplurality of data lines DL_R, DL_G, and DL_B, respectively. The redsub-pixel SEP_R includes two red sub-emission devices OLED_R1 andOLED_R2 by an anode split and a red pixel circuit PC_R. The greensub-pixel SEP_G includes two green sub-emission devices OLED_G1 andOLED_G2 by the anode split and a green pixel circuit PC_G. The bluesub-pixel SEP_B includes two blue sub-emission devices OLED_B1 andOLED_B2 by the anode split and a blue pixel circuit PC_B. Forconvenience of explanation and understanding, FIG. 39 shows only ananode of each sub-emission device.

Referring to FIG. 39 , the repair line RL is formed or located in apixel column direction to the left of the three emission sub-pixelsSEP_R, SEP_G, and SEP_B, and a first signal line GWL providing the firstcontrol signal GW, a second signal line GIL providing the second controlsignal GI, a third signal line GEL providing the third control signalGE, the power voltage line ELVDDL, an initialization voltage line VL,and the data lines DL_R, DL_G, and DL_B are formed or located in thepixel column direction to the right of the three emission sub-pixelsSEP_R, SEP_G, and SEP_B.

Each of the emission sub-pixels SEP_R, SEP_G, and SEP_B includes shortnodes SN1_R, SN1_G, and SN1_B that are provisionally coupled to therepair line RL, and cut nodes CN1_R, CN2_R, CN1_G, CN2_G, CN1_B, andCN2_B formed in electrode connection wirings coupling the redsub-emission devices OLED_R1 and OLED_R2, the green sub-emission devicesOLED_G1 and OLED_G2, and the blue sub-emission devices OLED_B1 andOLED_B2. The red sub-emission devices OLED_R1 and OLED_R2, the greensub-emission devices OLED_G1 and OLED_G2, and the blue sub-emissiondevices OLED_B1 and OLED_B2 may be separated or electrically isolatedfrom the red pixel circuit PC_R, the green pixel circuit PC_G, and theblue pixel circuit PC_B by cutting the circuit wirings 15 and 19 coupledto the red pixel circuit PC_R, the green pixel circuit PC_G, and theblue pixel circuit PC_B.

FIG. 40 is a plan view of the dummy pixel DP including the pixel circuit2E of FIG. 38 .

FIG. 40 shows the dummy pixel DP including the three dummy sub-pixelsSDP_R, SDP_G, and SDP_B that are coupled to the scan line SL and theplurality of data lines DL_R, DL_G, and DL_B, respectively. The reddummy sub-pixel SDP_R includes the red pixel circuit PC_R. The greendummy sub-pixel SDP_G includes the green pixel circuit PC_G. The bluedummy sub-pixel SDP_B includes the blue pixel circuit PC_B.

Referring to FIG. 40 , the repair line RL is formed or located in apixel column direction to the left of the three dummy sub-pixels SDP_R,SDP_G, and SDP_B. The first signal line GWL providing the first controlsignal GW, the second signal line GIL providing the second controlsignal GI, the third signal line GEL providing the third control signalGE, the power voltage line ELVDDL, the initialization voltage line VL,and the data lines DL_R, DL_G, and DL_B are formed or located in thepixel column direction to the right of the three dummy sub-pixels SDP_R,SDP_G, and SDP_B.

Each of the dummy sub-pixels SDP_R, SDP_G, and SDP_B includes shortnodes SN2_R, SN2_G, and SN2_B that are provisionally coupled to therepair line RL. The repair line RL is coupled to the power voltage lineELVDDL, and when a defective pixel is repaired by using the repair lineRL in the future, the power voltage line ELVDDL and the repair line RLmay be separated or electrically isolated from each other by cutting aregion X of the power connection wiring 18.

FIG. 41 is a plan view of the emission device E of the emission pixel EPaccording to another embodiment of the present invention. FIG. 42 is across-sectional view taken along a line C-C′ of FIG. 41 .

Referring to FIG. 41 , split electrodes of the emission device Eaccording to an embodiment of the present invention, i.e., the first andsecond anodes AD1 and AD2, the electrode connection wiring 11, and thecircuit connection wiring 12, may be integrally formed. The electrodeconnection wiring 11 may include the first connection units CU1 coupledto the first and second anodes AD1 and AD2 and the second connectionunit CU2 coupled to the circuit connection wiring 12. The first andsecond cut nodes CN1 and CN2 are formed between the first connectionunit CU1 and the second connection unit CU2. As such, the first andsecond cut nodes CN1 and CN2 may be cut by irradiating a laser beam ontothe first and second cut nodes CN1 and CN2 in the future. The electrodeconnection wiring 11 contacts the short wiring 14 that overlaps with apart of the repair connection wiring 13 in the first short node SN1 andis provisionally coupled to the repair connection wiring 13. The repairline RL is coupled to the repair connection wiring 13 through a contacthole. As such, the short wiring 14 and the repair connection wiring 13may be coupled to each other by irradiating the laser beam onto thefirst short node SN1 in the future.

The repair line RL and the short wiring 14 may be formed on the samelayer and of the same material as a conductive electrode included in aTFT of the pixel circuit PC, for example, a source electrode and a drainelectrode. The third insulating layer 105 is formed on the repair lineRL and the short wiring 14. The first and second anodes AD1 and AD2, theelectrode connection wiring 11, and the circuit connection wiring 12 areintegrally formed on the third insulating layer 105. The fourthinsulating layer 106 covering edges of the first and second anodes AD1and AD2 is formed on the first and second anodes AD1 and AD2.

FIG. 43 is a cross-sectional diagram of an organic light emittingdisplay apparatus including the emission pixels EP, according to anembodiment of the present invention.

Referring to FIG. 43 , the display area AA that includes the emissionpixels EP and displays an image are provided on the substrate 101 of theorganic light emitting display apparatus according to an embodiment ofthe present invention. In the non-display area NA outside the displayarea AA, the dummy pixel DP and a pad unit PAD that transfers aplurality of driving signals and control signals to the display area AAare formed. The emission pixels EP and the pad unit PAD are only shownin FIG. 43 .

The organic light emitting display apparatus includes the emissiondevices E including a plurality of sub-emission devices, the pixelcircuit PC including at least one TFT TR and at least one capacitor CAPand supplying a driving current to the emission device E, and the padunit PAD.

The emission device E includes an anode AD including the split first andsecond anodes AD1 and AD2, a cathode CD facing the anode AD, and anorganic layer OL including an emission layer formed or located betweenthe anode AD and the cathode CD.

The anode AD may have a three layer structure including semitransparentmetal and a transparent conductive oxide formed on top and bottomportions of the semitransparent metal and protecting the semitransparentmetal. The semitransparent metal may include silver (Ag) or a silveralloy. The transparent conductive oxide may include at least oneselected from the group consisting of ITO, IZO, ZnO, In₂O₃, IGO, andAZO. The semitransparent metal forms a micro-cavity structure along withthe cathode CD, thereby increasing light efficiency of the organic lightemitting display apparatus. The fourth insulating layer 106 that is apixel definition layer covering the split first and second anodes AD1and AD2 may be formed in edges of the split first and second anodes AD1and AD2. One of the split first and second anodes AD1 and AD2 may becoupled to one of a source electrode 217a and a drain electrode 217b ofthe transistor TR through a contact metal 117.

Although not shown, the split first and second anodes AD1 and AD2 may becoupled to each other by the electrode connection wiring 11 (see FIGS.15 and 41 ). The electrode connection wiring 11 may be formed on thesame layer and of the same material as the anode AD or may be formed onthe same layer and of the same material as an active layer 212 of thetransistor TR and contact the anode AD. The electrode connection wiring11 may contact one of the source electrode 217a and the drain electrode217b of the transistor TR. The transistor TR coupled to the electrodeconnection wiring 11 may be different from the transistor TR coupled toone of the split first and second anodes AD1 and AD2.

The cathode CD may be configured as a reflective electrode including areflective material. In this regard, the cathode CD may include at leastone selected from the group consisting of Al, Mg, Li, Ca, LiF/Ca, andLiF/Al. The cathode CD may be configured as a reflective electrode sothat light emitted from the organic layer OL is reflected from thecathode CD, and is transmitted through the anode AD formed ofsemitransparent metal, and then is emitted through the substrate 101.

The transistor TR may include the active layer 212 formed on the bufferlayer 102 of the substrate 101, a gate electrode 215 formed on theactive layer 212 with the first insulating layer 103 that is a gateinsulating layer formed therebetween and located at a locationcorresponding to a channel region 212c of the active layer 212, thesource electrode 217a and the drain electrode 217b disposed on the gateelectrode 215 with the second insulating layer 104 that is an interlayerinsulating layer formed or located therebetween and respectively coupledto a source region 212a and a drain region 212b.

The active layer 212 may be formed of a semiconductor containingamorphous or crystalline silicon, or an oxide semiconductor. The activelayer 212 may include the channel region 212c and the source region 212aand the drain region 212b that are doped with ion impurities and locatedat opposite sides of the channel region 212c. The gate electrode 215 maybe formed from a single layer or a plurality of layers including atleast one metal selected from the group consisting of aluminium (Al),platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au),nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li),nickel (Ni), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W),and copper (Cu). The source electrode 217a and the drain electrode 217bmay be formed from two or more layers of two different metals withdifferent electron mobilities. For example, the two different metals maybe selected from the group consisting of Al, Pt, Pd, Ag, Mg, Au, Ni, Nd,Ir, Cr, Li, Ni, Ca, Mo, Ti, W, Cu, or an alloy thereof.

The capacitor CAP may include a first electrode 312 formed on the samelayer as the active layer 212, a second electrode 314 formed on the samelayer as the gate electrode 215, and a third electrode 317 formed on thesame layer as the source electrode 217a and the drain electrode 217b.

The first electrode 312 of the capacitor CAP may be formed of asemiconductor doped with ion impurities like the source region 212a andthe drain region 212b of the active layer 212. The second electrode 314of the capacitor CAP is formed on the first insulating layer 103 wherethe gate electrode 215 is formed or located, but of a different materialthan the gate electrode 215. The second electrode 314 may include atransparent conductive oxide. The capacitor CAP may have ametal-insulator-metal (MIM) structure by forming a semiconductor dopedwith ion impurities as the first electrode 312 through the secondelectrode 314.

First and second pad electrodes 417 and 418 that are connectionterminals of an external driver may be formed in the pad unit PAD.

The first pad layer 417 may include a plurality of metal layers withdifferent electron mobilities. For example, the first pad layer 417 maybe formed from multiple layers of at least one metal selected from thegroup consisting of Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ni, Ca,Mo, Ti, W, and Cu.

The second pad layer 418 may be formed of a transparent conductive oxidecontaining at least one material selected from the group consisting ofITO, IZO, ZnO, In₂O₃, IGO, and AZO. The second pad layer 418 may preventexposure of the first pad layer 417 to moisture and oxygen, therebypreventing degradation in reliability of a pad.

In the above-described embodiments, a pixel circuit is formed as ap-channel metal-oxide semiconductor (PMOS) transistor and a low-levelsignal is an enable signal while a high-level signal is a disablesignal. However, the present invention may also be applied by formingthe pixel circuit as an n-channel metal-oxide semiconductor (NMOS)transistor and inverting the provided signals. In this case, ahigh-level signal is an enable signal and a low-level signal is adisable signal.

In the above-described embodiments, an emission pixel circuit and adummy pixel circuit may be the same (e.g., having a same componentstructure or functionality), or the dummy pixel circuit may be different(e.g., having a different component structure or functionality) from theemission pixel circuit of which TFTs and/or capacitors are partiallyomitted and/or added.

In the above-described embodiments, although an anode has a two splitstructure, the anode may have a plural split structure, for example,three split anodes, four split anodes, etc., as described above.

According to embodiments of the present invention, an operating point ofa TFT is included in a saturation range and, if an anode of a defectivepixel has a high resistance, a current of the defective pixel may becorrected by predicting a resistance value.

The embodiments of the present invention are not limited to theabove-described pixel structure and driving method, may be applied tovarious pixels for emitting light by using various methods, and mayachieve light emission without any perceivable brightness reduction byrepairing a bright spot or a dark spot of a defective pixel due to adefect of a pixel circuit or an emission device.

A dark spot or a dark spot caused by a defective pixel circuit oremission device is relatively easily repaired by using a dummy pixel ofa display apparatus of the present invention, thereby improving yieldand reliability of a panel.

While the present invention has been particularly shown and describedwith reference to exemplary embodiments thereof, it will be understoodby those of ordinary skill in the art that various changes in form anddetails may be made therein without departing from the spirit and scopeof the present invention as defined by the following claims, and theirequivalents.

What is claimed is:
 1. An organic light-emitting display apparatuscomprising: an emission pixel comprising an emission device comprising aplurality of sub-emission devices and an emission pixel circuitconnected to a first scan line and a data line, in a display area; adummy pixel comprising a dummy pixel circuit connected to a second scanline being different from the first scan line and the data line, in anon-display area around the display area; and a repair line extendingacross a column or a row in the display area to the non-display area,wherein the repair line is insulated from the emission device and theemission pixel circuit of the emission pixel and the dummy pixelcircuit.
 2. The organic light-emitting display apparatus of claim 1,wherein each of the plurality of sub-emission devices comprises: a lowerelectrode among a plurality of separated lower electrodes; an upperelectrode commonly facing the plurality of separated lower electrodes;and an emission layer between the lower electrode and the upperelectrode, wherein the plurality of separated lower electrodes areelectrically coupled to each other through an electrode connectionwiring.
 3. The organic light-emitting display apparatus of claim 2,wherein the electrode connection wiring comprises at least one of metal,amorphous silicon, crystalline silicon, and an oxide semiconductor. 4.The organic light-emitting display apparatus of claim 2, wherein theelectrode connection wiring is at a same layer and of a same material asan active layer of the emission pixel circuit.
 5. The organiclight-emitting display apparatus of claim 2, wherein the electrodeconnection wiring is integrally formed with the plurality of separatedlower electrodes.
 6. The organic light-emitting display apparatus ofclaim 2, wherein the electrode connection wiring comprises: a pluralityof first connection units coupled to the plurality of separated lowerelectrodes; a second connection unit coupled to the emission pixelcircuit; and a plurality of cut nodes between the first connection unitsand the second connection unit.
 7. The organic light-emitting displayapparatus of claim 6, further comprising: at least one circuit wiringhaving one end coupled to the emission pixel circuit and another endcoupled to the second connection unit.
 8. The organic light-emittingdisplay apparatus of claim 6, further comprising: a first repairconnection wiring having one end coupled to the repair line and anotherend overlapping with a first short wiring coupled to one of the firstconnection units; and an insulating layer between the first repairconnection wiring and the first short wiring.
 9. The organiclight-emitting display apparatus of claim 8, wherein each of the firstrepair connection wiring and the first short wiring are at a same layerand of a same material as respective conductive layers formed ondifferent layers of the emission pixel circuit.
 10. The organiclight-emitting display apparatus of claim 1, wherein the dummy pixelcircuit is on at least one row among first and last rows of each column.11. The organic light-emitting display apparatus of claim 1, wherein theemission pixel circuit and the dummy pixel circuit have a same componentstructure or function.
 12. The organic light-emitting display apparatusof claim 1, further comprising: a second repair connection wiring havingone end coupled to the repair line and another end overlapping with asecond short wiring coupled to the dummy pixel circuit; and aninsulating layer is between the second repair connection wiring and thesecond short wiring.
 13. The organic light-emitting display apparatus ofclaim 1, wherein the repair line is coupled to a power voltage linethrough a power connection wiring.
 14. The organic light-emittingdisplay apparatus of claim 1, wherein the emission pixel circuitcomprises: a first transistor configured to transfer a data signal inresponse to a scan signal; a capacitor configured to be charged with avoltage corresponding to the data signal; and a second transistorconfigured to transfer a driving current corresponding to the voltagecharged in the capacitor to the emission device.
 15. The organiclight-emitting display apparatus of claim 1, wherein the emission pixelcircuit further comprises: a first transistor configured to receive adata signal from the data line in response to a scan signal; a secondtransistor configured to transfer a driving current corresponding to thedata signal to the emission device; a third transistor configured todiode-connect the second transistor; a first capacitor configured to becharged with a voltage corresponding to the data signal; and a secondcapacitor connected to one electrode of the first capacitor and a gateelectrode of the second transistor.
 16. The organic light-emittingdisplay apparatus of claim 15, wherein the emission pixel circuitfurther comprises: a fourth transistor connected to between the firsttransistor and the one electrode of the first capacitor; a fifthtransistor connected to between the data line and the one electrode ofthe first capacitor; and a third capacitor having one electrodeconnected to a node between the first transistor and the fourthtransistor and another electrode connected to a gate electrode of thefifth transistor.
 17. The organic light-emitting display apparatus ofclaim 1, wherein the emission pixel circuit further comprises: a firsttransistor configured to receive a data signal from the data line inresponse to a scan signal; a second transistor configured to transfer adriving current corresponding to the data signal to the emission device;a third transistor configured to diode-connect the second transistor; afourth transistor connected to between the first transistor and thesecond transistor; a fifth transistor connected to between the secondtransistor and the emission device; a sixth transistor connected tobetween a gate electrode of the second transistor and an initial power;a first capacitor connected to between the gate electrode of the secondtransistor and a first power source; and a second capacitor having oneelectrode connected to a node between the first transistor and thefourth transistor and another electrode connected to a second powersource.
 18. The organic light-emitting display apparatus of claim 1,wherein the plurality of sub-emission devices comprises: a firstsub-emission device comprising a first lower electrode, an upperelectrode facing the first lower electrode, and a first emission layerbetween the first lower electrode and the upper electrode; and a secondsub-emission device comprising a second lower electrode, the upperelectrode facing the second lower electrode, and a second emission layerbetween the second lower electrode and the upper electrode, wherein thefirst lower electrode and the second lower electrode are coupled to eachother through an electrode connection wiring.
 19. The organiclight-emitting display apparatus of claim 18, wherein the electrodeconnection wiring comprises: a first connection unit coupled to thefirst lower electrode; a second connection unit coupled to the secondlower electrode; a third connection unit coupled to the emission pixelcircuit; a first node between the first connection unit and the thirdconnection unit; and a second node between the second connection unitand the third connection unit.
 20. The organic light-emitting displayapparatus of claim 18, further comprising: a first repair connectionwiring having one end coupled to the repair line and another endoverlapping with a first short wiring coupled to a first connectionunit; a first insulating layer between the first repair connectionwiring and the first short wiring; a second repair connection wiringhaving one end coupled to the repair line and another end overlappingwith a second short wiring coupled to the dummy pixel circuit; and asecond insulating layer between the second repair connection wiring andthe second short wiring.
 21. The organic light-emitting displayapparatus of claim 1, wherein at least one sub-emission device of theemission pixel is separated from the emission pixel circuit of theemission pixel.
 22. An organic light-emitting display apparatuscomprising: an emission pixel in a display area, the emission pixelcomprising an emission device comprising a plurality of sub-emissiondevices and an emission pixel circuit connected to a first scan line anda data line; a dummy pixel in a non-display area, the dummy pixelcomprising a dummy pixel circuit connected to a second scan line beingdifferent from the first scan line and the data line; and a repair lineextending across a column or a row in the display area to thenon-display area, and coupled to a sub-emission device of thesub-emission devices of the emission pixel and the dummy pixel circuitof the dummy pixel.
 23. The organic light-emitting display apparatus ofclaim 22, wherein the repair line is coupled to the emission device ofthe emission pixel and the dummy pixel circuit of the dummy pixel. 24.The organic light-emitting display apparatus of claim 23, wherein thesub-emission devices of the emission pixel are separated from theemission pixel circuit.
 25. The organic light-emitting display apparatusof claim 23, wherein at least one sub-emission device of the emissionpixel is electrically coupled to the repair line and is separated fromthe emission pixel circuit, and the rest of the sub-emission devices ofthe emission pixel are electrically coupled to the emission pixelcircuit and are separated from the repair line.
 26. The organiclight-emitting display apparatus of claim 25, wherein the dummy pixelcircuit of the dummy pixel is configured to supply a driving current tothe at least one sub-emission device of the emission pixel, and theemission pixel circuit of the emission pixel is configured to supply adriving current to the rest of the sub-emission devices of the emissionpixel.
 27. The organic light-emitting display apparatus of claim 23,wherein the dummy pixel circuit of the dummy pixel is configured tosupply a driving current to the emission device of the emission pixel ata predetermined time.
 28. The organic light-emitting display apparatusof claim 23, wherein a data signal supplied to the dummy pixel circuitof the dummy pixel and a data signal supplied to the emission pixelcircuit of the emission pixel are the same.
 29. A display apparatuscomprising: a first pixel circuit connected to a first scan line and adata line in a display area; a first electrode electrically coupled tothe first pixel circuit in the display area; a second pixel circuitconnected to a second scan line being different from the first scan lineand the data line in a non-display area around the display area; aconductive pattern in a layer different from the first electrode, theconductive pattern comprising a repair line extending across a column ora row from the display area to the non-display area, the repair linebeing insulated from the first pixel circuit and the second pixelcircuit; and a first connection member electrically coupled to the firstelectrode and the first pixel circuit, the first connection memberoverlapping a portion of the conductive pattern in a plan view andinsulated from the overlapped portion of the conductive pattern.
 30. Thedisplay apparatus of claim 29, wherein the first connection member isbetween the first electrode and the conductive pattern in across-sectional view.
 31. The display apparatus of claim 29, furthercomprising a second connection member electrically coupled to the secondpixel circuit and overlapping a portion of the conductive pattern. 32.The display apparatus of claim 29, further comprising: an emission layeron the first electrode; and a second electrode on the emission layer andfacing the first electrode.
 33. The display apparatus of claim 29,wherein the first connection member is on a same layer as a sourceelectrode and a drain electrode of a thin film transistor included inthe first pixel circuit.
 34. The display apparatus of claim 29, whereinthe first connection member comprises a first layer comprising titaniumand a second layer comprising aluminum.
 35. The display apparatus ofclaim 29, wherein a portion of the conductive pattern that overlaps thefirst connection member comprises molybdenum.
 36. The display apparatusof claim 29, wherein the conductive pattern further comprises aconnection wiring electrically coupled to the repair line, and wherein aportion of the conductive pattern that overlaps the first connectionmember comprises a portion of the connection wiring.
 37. The displayapparatus of claim 29, wherein the conductive pattern further comprisesa connection wiring electrically coupled to the repair line, and whereina portion of the repair line overlaps a portion of the connectionwiring.
 38. The display apparatus of claim 29, wherein a portion of thefirst connection member that overlaps the conductive pattern is spacedapart from a portion of the first connection member that contacts thefirst electrode via an opening.
 39. The display apparatus of claim 29,wherein the conductive pattern is electrically coupled to a powervoltage line electrically coupled to the first pixel circuit.
 40. Thedisplay apparatus of claim 29, wherein the first scan line extends in afirst direction, and wherein the data line extends in a second directiondifferent from the first direction.
 41. The display apparatus of claim40, wherein the conductive pattern is parallel with the first scan line.42. The display apparatus of claim 40, wherein the conductive pattern isparallel with the first data line.
 43. The display apparatus of claim29, further comprising: a first connection wiring electrically coupledto the first pixel circuit; and a second connection wiring electricallycoupled to the first connection member and the first connection wiring.44. A display apparatus comprising: a first pixel circuit connected to afirst scan line and a data line in a display area; a second pixelcircuit connected to a second scan line being different from the firstscan line and the data line in a non-display area around the displayarea; a first electrode in the display area; a conductive pattern in alayer different from the first electrode, the conductive patterncomprising a repair line extending across a column or a row from thedisplay area to the non-display area; and a first connection memberbetween the first electrode and the conductive pattern in across-sectional view, and electrically coupled to the first electrodeand the conductive pattern.
 45. The display apparatus of claim 44,wherein the first pixel circuit is disconnected from the firstelectrode.
 46. The display apparatus of claim 45, wherein the firstconnection member is on a same layer as a source electrode and a drainelectrode of a thin film transistor included in the first pixel circuit.47. The display apparatus of claim 44, further comprising a secondconnection member electrically coupled to the second pixel circuit andthe conductive pattern.
 48. The display apparatus of claim 44, furthercomprising: an emission layer on the first electrode; and a secondelectrode on the emission layer and facing the first electrode.
 49. Thedisplay apparatus of claim 44, wherein the first connection membercomprises a first layer comprising titanium and a second layercomprising aluminum.
 50. The display apparatus of claim 44, wherein aportion of the conductive pattern that overlaps and is electricallycoupled to the first connection member comprises molybdenum.
 51. Thedisplay apparatus of claim 44, wherein the conductive pattern furthercomprises a connection wiring electrically coupled to the repair line,and wherein a portion of the conductive pattern that overlaps and iselectrically coupled to the first connection member comprises a portionof the connection wiring.
 52. The display apparatus of claim 44, whereinthe first scan line extends in a first direction, and wherein the dataline extends in a second direction different from the first direction.53. The display apparatus of claim 52, wherein the conductive pattern isparallel with the first scan line.
 54. The display apparatus of claim52, wherein the conductive pattern is parallel with the first data line.